1. The Field of the Invention
The present invention relates to semiconductor chip packaging. More particularly, the present invention relates to realigning and reshaping of solder balls or conductive bumps in an array upon a chip or die prior to final packaging. In particular, the present invention relates to a solder ball shaping tool and a method of using the tool to reshape and realign solder balls in an array that may have been misaligned either during solder ball deposition or during handling.
2. The Relevant Technology
In the field of chip packaging, a goal for those skilled in the art is to miniaturize the chip package, such as in chip scale packages (CSP) where the chip itself is not much smaller than its package. Various methods have been proposed to eliminate wire bonding and to achieve lead on chip (LOC) wiring as a means of decreasing chip packaging size. Traditionally, connections have been achieved by connecting a bonding wire from a bonding pad on the chip to a lead finger. However, wire bonding is time consuming and costly, particularly as the number of inputs and outputs from a single chip increases.
As integrated circuit technology advances, other methods of connecting input and output from a chip to the external world must be explored to facilitate miniaturization. Solder balls, also called solder bumps, are generally intended to all be of substantially the same size. For example, the solder balls may be about 0.3 to 0.4 millimeters in diameter where they contact the bottom of the package surface. Generally an array of electrical contacts congruent to the solder ball array is to be found on a circuit board to which the package is to be mounted. The solder balls individually contact their corresponding pads on the circuit board. In order to assure adequate contact, solder paste is often required to acconunodate for variations and discrepancies between solder ball sizes and solder ball locations. After contact, the circuit board and the chip are placed in a solder reflow furnace, under conditions sufficient to cause the solder ball to reflow and coalesce within the solder paste in order to form an adequate electrical connection.
One method of forming solder paste on a printed circuit board (PCB) is to use silk-screening techniques to deposit solder paste onto the PCB. Where a silk-screening stencil is substantially adequate in its location of positioning solder paste onto the PCB, the problem of getting substantially uniform solder paste bumps remains, due to uneven distribution of solder paste and pressures during the silk-screening process. An alternative method of depositing solder paste is multi-point deposition of solder paste globules. As each solder paste globule is deposited, size variations occur that may cause shorting between neighboring sites.
One method of forming solder bumps comprises stencil or screen printing or dispensing of solder paste in a desired pattern on the package substrate followed by reflowing to provide rounded solder bumps. Maintaining accurate placement of the chip is difficult and the reliability of electrical connections between solder bumps and contact pads is reduced due to misplacement of the solder bumps. Additionally, variation in location in discrepancy in shape of solder bumps makes it difficult and time consuming to effectively make all electrical connections.
Conventionally, solder bump reflowing is used to mount a chip or chip package onto a PCB. A degree of dimensional variation occurs with solder bumps in the prior art. Reliability in the mounting and electrical connection of integrated circuit packages to their mounting boards is important because the solder joints between the contacts of the chip and those of the circuit board are highly difficult to visually inspect and non-destructively test once the chip is in place on the PCB. Although statistical methods of quality control along with destructive testing methods must be relied upon to provide confidence that reliable electrical connections are being made, more effective methods are being sought.
PCBs are typically made of laminated layers and organic resins. Plastic or organic substrates have a drawback of dimensional instability such as warpage and bowing. Warpage and bowing cause additional challenges in effectively making electrical connection between the PCB and the chip package. When an integrated circuit package with an array of solder balls is placed against a PCB, if the package and PCB are sufficiently coplanar, then each of the solder balls will contact its corresponding contact pad.
A bowed or warped PCB or integrated circuit package may be sufficiently deformed so as to prevent effective electrical contact between solder paste and the solder balls. FIG. 1 illustrates one of the problems associated with a bowed or warped chip package. In an exaggerated illustration seen in FIG. 1, integrated circuit package 10 containing a chip 8 is shown as being warped when viewed in cross-section. In FIG. 1 it can be seen that integrated circuit package 10 is being placed in proximity to a PCB 16. Upon PCB 16 there is an array of pads 18 that correspond to an array of solder balls 12 upon integrated circuit package 10. Solder ball 12 is disposed upon a lower surface 14 of integrated circuit package 10 in an array that follows the warpage thereof. It can be seen that a degree of warpage, W, may be quantified as approximately the distance between a low spot, L, on lower surface 14 and approximately the center of integrated circuit package 10. It can be seen that upon assembly of integrated circuit package 10 with PCB 16, low spot L will likely contact PCB at a corresponding pad 18 but a high spot, H on lower surface 14, will likely not make contact thereto. An attempt to force PCB 16 into high spot H may cause solder ball 12 at low spot L to substantially flatten to the point that it will short into an adjacent solder ball. Reduction of size of solder ball 12 may alleviate the problem of solder ball flattening and subsequent shorting into an adjacent solder ball. However, reduction of size of solder ball 12 in the area of high spot H will likely prevent making an electrical contact to PCB 16.
In an attempt to compensate for a warped integrated circuit package, a larger solder ball may be deposited. However, as the pitch between adjacent solder balls in a ball grid array (BGA) decreases due to smaller packaging techniques, a larger solder ball that is substantially flattened during mating of a BGA to a pad array, in relationship to other solder balls, may cause a short between solder balls. Thus, non-planarity of both the PCB and integrated circuit package and dimensional variability of solder balls among themselves all contribute to the problem of defectively connecting a chip package to a PCB.
In situations where a BGA is uniformly and substantially precisely set down upon a grid within design tolerances, subsequent handling steps can damage, deform and displace any or all of the solder balls. In FIG. 1, it can be seen that a design distance, d.sub.0 describes spacing between two solder balls 12. Displacement of a solder ball during subsequent handling steps will cause variations such as a spacing less than d.sub.0, d.sub.1, and a spacing greater than d.sub.0, d.sub.2.
Handling steps include chip singulation, marking, and testing such as burn-in. One technique that has been used in the prior art to reclaim the design shape of a solder ball is to reflow the solder ball through a thermal process. One problem with a thermal reflow process is that a given chip or array thereof may be at or near the end of its fabrication processing thermal budget and any further thermal processing will compromise the quality or reliability of the chip or chip array.
What is needed in the art is a tool that effectively shapes and sizes solder balls. What is also needed in the art is a tool that effectively restores shapes and sizes of individual solder balls within an array to their designed location and height to prevent electrical shorting inherent in smaller packaging and increasingly finer pitch of solder balls.